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E2U0036-28-81 Semiconductor
Semiconductor MSM7583
p/4 Shift QPSK MODEM
This version: Aug. 1998 MSM7583 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7583 is a CMOS IC for the p/4 shift QPSK modem developed for the digital cordless telephone systems. The device, which contains one system of modulator and two systems of demodulater, is optimized for applications for cell stations in a cordless telephone system.
FEATURES
* Single +5 V Power Supply: 4.5 V to 5.5 V (Modulator Block) * Built in Root Nyquist Filter for Baseband Limitting (50% Roll-off) * Ramp Bit for Burst Signal Rise-up (Fall-down) : 2 Symbols * Built-in D/A converters for Analog Outputs of Quadrature Signal I/Q Components and I 2 + Q 2 (Analog) Power Envelope Output. * Differential I/Q Analog Output Type * I/Q Output, DC Offset/Amplitude Adjustable (Demodulator Block) * Built-in Diversity-corresponding Demodulation Circuit: 2 Systems * Full Digital p/4 Shift QPSK Demodulation System * Input IF Signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz * Built-in Clock Recovery: 4 Circuits * Transmit/Receive Independent Power-down Control capability * Built-in Precise Analog Voltage Reference * MCU Serial Interface for Mode Setting and Built-in Test Circuit * Test Modes: Eye Pattern/AFC Compensating Signal/Phase Detection Signal Monitoring Capability * Transmission Speed: 384 kbps * Low Power Consumption Operating Mode: 16 mA Typ./Modulator (VDD = 5.0 V) 28 mA Typ./Demodulator (VDD = 5.0 V) Whole Power-down Mode: 0.03 mA Typ. (VDD = 5.0 V) * Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK)(Product name : MSM7583GS-BK)
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Semiconductor
MSM7583
BLOCK DIAGRAM
VDD DGND AGND
SLS11 SLS21
SL41 SL41 SL41 SL41
AFC1
RXD1
IFIN1
Phase Detector
IFSEL0 (From CR)
Delay Detector
AFC
Decision
RXC1 RXSC1
MCK IFCK
S E L
RCW1 RPR1 IFSEL1 (From CR) To each block
SL11 SL21 SL31 SL41
X2 X1 DEN EXCK DIN DOUT
D E C
DPLL
S E L
Control Register
SL11 To each block
S E L D E
SL21 SL31 SL41
RXD0 RXC0 RXSC0 RXSEL
DPLL
PDN0 PDN1 PDN2 RESET
C
S E L
RPR2 RCW2 RXCS2 RXC2 RXD2 AFC2 SLS21 SLS22
IFN2
Phase Detector
Delay Detector
AFC
Decision
SL42
SL32
SL22
BST0 I+ I- Q+ Q- +1 -1 +1 -1
DC Offset Adjust DC Offset Adjust
SL12
LPF
I output gain adjust
D/A
Root Nyquist LPF
S/P MAPPING
TXD TXW
LPF
D/A
3.84 MHz To D/A
Q output gain adjust
S E L
PLL
TXCI
1/10 ENV SG +1 VREF
To internal SG
LPF
D/A
To monitor output of each block TEST1, TEST0 (From CR)
384 kHZ
TXCO
TXCEL (From CR)
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Semiconductor
MSM7583
PIN CONFIGURATION (TOP VIEW)
55 RXSC0
51 RXSC2
52 RXSEL
59 RCW2
56 RCW1
61 RPR2
58 RPR1
53 RXD0
NC 1 IFCK 2 MCK 3 DGND 4 IFIN2 5 DGND 6 IFIN1 7 DGND 8 VDD 9 DOUT 10 DIN 11 EXCK 12 DEN 13 RESET 14 PDN0 15 PDN1 16
NC 17 PDN2 18 BSTO 19 TXW 20 TXD 21 TXCO 22 TXCI 23 NC 24 NC 25 NC 26 NC 27 NC 28 NC 29 NC 30 NC 31 NC 32
49 RXD2
54 RXC0
50 RXC2
60 AFC2
57 AFC1
64 NC
63 X2
62 X1
48 NC 47 SLS22 46 SLS12 45 RXSC1 44 RXC1 43 RXD1 42 SLS21 41 SLS11 40 VDD 39 ENV 38 Q- 37 Q+ 36 I- 35 I+ 34 SG 33 AGND
64-Pin Plastic QFP
NC : No connect pin
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Semiconductor
MSM7583
PIN AND FUNCTIONAL DESCRIPTIONS
TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CR0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because this device uses APLL to generate internal clock pulses. When CR0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied to TXCI, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the TXCI input by 10. The transmit data, synchronous 384 kHz clock pulse, should be input to the TXD. In this case the device does not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CR0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CR0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) TXW Transmit data window signal input. The transmit timing signal for the burst data is input to the device through this pin. If TXW pin is "1", modulation data is output. (Refer to Fig. 1.) I+, I- Quadrature modulation signal I component differential analog outputs. The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control registers CR1 - B7 to B4, and the offset voltage at the I- pin can be adjusted using CR3 - B7 to B3. Q+, Q- Quadrature modulation signal Q component differential analog outputs. The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load conditions are: R 10 kW , C 20 pF. The gain of these pins can be adjusted using the control registers CR1 - B3 to B0, and the offset voltage at the Q- pin can be adjusted using CR4 - B7 to B3.
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Semiconductor ENV
MSM7583
Quadrature modulation signal envelope ( I 2 + Q 2 ) output. Its output level is 500 mVpp with 1.6 Vdc as a center value. The output pin load conditions are: R 10 kW , C 20 pF. The gain of this output can be adjusted using the control registers CR2 - B7 to B4. This pin is also used to monitor eye pattern, AFC compensating signal, and phase detection of the demodulator block during the test mode. Refer to the description of the control register for details. BSTO Modulation burst window signal output. The burst position for the I/Q baseband modulation output is output. (Refer to Fig. 1.)
(1) CR0 - B6 ="0". TXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13 Dn-1 Dn
Ramp rise-up 2 symbols Delay of 6.25 symbols (2) CR0 - B6 ="1". TXD TXCI (3.84 MHz) TXW TXCO (384 kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13 Dn-1 Dn
Ramp fall-down 2 symbols Delay of 6.25 symbols
Ramp rise-up 2 symbols Delay of 6.25 symbols TXCI (384 kHz) TXW BSTO
Ramp fall-down 2 symbols Delay of 6.25 symbols
1
2
8
9
10
N
N+1
N+2
N+16
N+17
N+18
N+19
Figure 1 Transmitter Timing Diagram
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Semiconductor SG
MSM7583
Internal reference voltage output. The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and the AGND pin. The external SG voltage, if necessary should be used via buffer. RESET Control register reset. When this pin is set to "0", the register is reset to the initial value. The reset signal input width is 200 ns or more. PDN0, PDN1, PDN2 Inputs for power-down control. PDN0 controls the standby/communication modes, PDN1 controls the modulator, and PDN2 controls the demodulator. Refer to Table 1 for details. Table 1 Power Down Control
PDN0 PDN1 PDN2 0 Standby Mode 0 -- -- 0 1 All power-down. Modulator power is off (VREF and PLL power is also off). Demodulator power is on. Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Only demodulator clock recovery block power is on. Modulator power is on. Only demodulator clock recovery block power is on. Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Demodulator power is on. Modulator power is on. Demodulator power is on. Function Mode Mode A Mode B Mode C Mode D Mode E Mode F
1 1 1 1
0 1 0 1
0 0 1 1
Communication Mode
VDD +5 V power supply voltage. AGND Analog signal ground. DGND Digital signal ground. AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on the PCB as close as possible from the device. AGND and DGND should be connected as close as prossible on the PC board.
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Semiconductor MCK Master clock input. The clock frequency is 19.2 MHz. IFIN1, IFIN2
MSM7583
Modulated signal inputs for the demodulator block. Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz based on CR0 - B4 and B3. IFIN1 is for Channel 1, and IFIN2 for Channel 2. IFCK Clock signal input for demodulator block IF frequency (10.7 MHz or 10.75 MHz). If the IF frequency is 10.7 MHz, 19.0222 MHz should be supplied. When it is 10.75 MHz, 19.1111 MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When supplying a 19.0222 MHz or 19.1111 MHz clock to IFCK, use these pins. (Refer to Fig. 2.)
When IFIN = 10.7 MHz or 10.75 MHz
When IFIN = 1.2 MHz or 10.8 MHz
MSM7583 X1 X2 IFCK X1
MSM7583 X2 IFCK
19.0222 MHz or 19.1111 MHz
Figure 2 How to Use IFCK, X1, and X2
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Semiconductor
MSM7583
RXD1, RXC1, RXSC1 Channel 1 receive data, receive clock, and receive symbol clock output pins. During power-on, these output pins are at the output level of the clock recovery circuit selected by a combination of SLS11 and SLS21 (described later). (Refer to Fig. 3.) RXD2, RXC2, RXSC2 Channel 2 receive data, receive clock, and receive symbol clock output pins. During power-on, these output pins are at the output level of the clock recovery circuit selected by a combination of SLS12 and SLS22 (described later). (Refer to Fig. 3.) SLS11, SLS21, SLS12, SLS22 Receiver slot select signal pins of Channel 1 (SLS11, SLS21) and Channel 2 (SLS12, SLS22). The MSM7583 has four sets of clock recovery circuits and four AFC information storage registers. One of the sets is selected according to a combination of the signals at these pins. (Refer to Fig. 3.) Channel 1 (SLS21, SLS11) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 Channel 2 (SLS22, SLS12) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4
RXD1 (RXD2) RXC1 (RXC2) RXSC1 (RXSC2) SLS21 (SLS22) SLS11 (SLS12) The recovery data and clock pulse are selected asynchronously by the SLS signals.
Figure 3 RXD, RXC, and RXSC Timing Diagram RXD0, RXC0, RXSC0 Receive data, receive clock, and receive symbol clock outputs. These pins are at the output level selected by RXSEL (described below).
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Semiconductor RXSEL
MSM7583
Receive data, receive clock, and receive symbol clock select signal. If this pin is set to "0", the output levels of Channel 1 RXD1, RXC1, and RXSC1 are selected to be output to RXD0, RXC0, and RXSC0. If this pin is set to "1", the output levels of Channel 2 RXD2, RXC2, and RXSC2 are selected to be output to RXD0, RXC0, and RXSC0. Note that a hazard may sometime occur in RXDO, RXCO, and RXSCO because RXSEL selects asynchronously. RPR1, RPR2 High-speed phase clock control signal input pin for the clock recovery circuit. When each of the pins is "1", the clock recovery circuit starts in the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. When each of the pins is "0", the circuit is always in the lowspeed phase clock mode. RPR1 is for Channel 1, and RPR2 for Channel 2. AFC1, AFC2 AFC operation range specification signal inputs. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC operation starts at a certain period after the AFC information is reset. When RPR is set to "1", an average number of times that AFC sets to on is low. When RPR is "0", it is high. When AFC is "0", frequency error is not calculated, but the frequency is corrected using an error that is held. AFC1 is for Channel 1, and AFC2 for Channel 2. RCW1, RCW2 Clock recovery circuit operation ON/OFF control signal inputs. When this pin is "0", DPLL does not make any phase corrections. RCW1 is for Channel 1, and RCW2 for Channel 2.
(CASE1) AFC RPR Average number of times AFC information Average AFC is high. is reset. number of times AFC is low. (CASE2) AFC RPR "0" Average number of times The clock recovery AFC is high. circuit starts with the previous AFC information. AFC information is maintained. AFC information is maintained.
Figure 4 AFC Control Timing Diagram
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Semiconductor DEN, EXCK, DIN, DOUT
MSM7583
Serial control ports for the microprocessor interface. The MSM7583 contains a 6-byte control register. An external CPU uses these pins to read data from and write data to the control register. DEN is the "Enable" signal input pin. EXCK is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output pin. Figure 5 shows an input/output timing diagram.
, ,
DEN EXCK DIN W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 DOUT High Impedance (a) Data Write Timing Diagram DEN EXCK DIN R A2 A1 A0 DOUT High Impedance B7 B6 B5 B4 B3 B2 B1 B0 (b) Data Read Timing Diagram
Figure 5 MCU Interface Input/Output Timing Diagram
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Semiconductor The register map is shown below Table 2 Control Register Map
Register CR0 CR1 CR2 CR3 CR4 CR5 Address A2 A1 A0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 B7 B6 B5 B4 Data B3 B2 B1 B0 TEST0 Qch GAIN0 -- -- -- ICT0 ENVPD TXCSEL MODOFF IFSEL1 IFSEL0 ENVSEL TEST1 Qch Qch Qch Ich Ich Ich Ich GAIN3 GAIN2 GAIN1 GAIN0 GAIN3 GAIN2 GAIN1 ENV GAIN3 ENV GAIN2 ENV GAIN1 ENV GAIN0 -- -- -- -- LOCAL INV0 -- -- -- ICT1
MSM7583
R/W R/W R/W R/W R/W R/W R/W
Ich Ich Ich Ich Ich Offset4 Offset3 Offset2 Offset1 Offset0 Qch Qch Qch Qch Qch Offset4 Offset3 Offset2 Offset1 Offset0 ICT7 ICT6 ICT5 ICT4 LOCAL INV1
R/W : Read/Write enable
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Semiconductor
MSM7583
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Storage Temperature Symbol VDD VDIN TSTG Condition -- -- -- Rating 0 to 7 -0.3 to VDD + 0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Master Clock Frequency Modulator Input Frequency Demodulator Input Frequency Clock Duty Cycle IF Input Duty Cycle Symbol VDD Ta VIH VIL fMCK fTXC1 fTXC2 fIFCK1 fIFCK2 DCCK DCIF Condition Voltage must be fixed -- All digital input pins All digital input pins MCK TXCI (when CR0 - B6 = "0") TXCI (when CR0 - B6 = "1")
(VDD = 4.5 V to 5.5 V, Ta = -25C to +70C) Min. 4.5 -25 2.2 0 -- -- -- Typ. -- +25 -- -- 19.2 384 3.84 Max. 5.5 +70 VDD 0.6 -- -- -- Unit V C V V MHz kHz
IFCK (when IFIN = 10.7 MHz) IFCK (when IFIN = 10.75 MHz) MCK, IFCK, TXCI IFCK
-50 ppm 19.0222 -50 ppm 19.1111 40 45 50 50
MHz +50 ppm MHz +50 ppm MHz 60 55 % %
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter Symbol Condition IDD1 Mode A (when VDD = 5.0 V) IDD2 Mode B (when VDD = 5.0 V) IDD3 Power Supply Current IDD4 IDD5 IDD6 Output High Voltage Output Low Voltage Input Leakage Current VOH VOL IIH IIL Mode C (when VDD = 5.0 V) Mode D (when VDD = 5.0 V) Mode E (when VDD = 5.0 V) Mode F (when VDD = 5.0 V) IOH = 0.4 mA IOL = -1.6 mA -- -- (VDD = 4.5 V to 5.5 V, Ta = -25C to +70C) Min. -- -- -- -- -- -- 2.8 0.0 -- -- Typ. 0.03 25.0 8.5 16.0 28.0 35.0 -- -- -- -- Max. 0.06 50.0 17.0 32.0 56.0 70.0 VDD 0.4 10 10 Unit mA mA mA mA mA mA V V mA mA
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Semiconductor Analog Interface Characteristics
Parameter Output Resistance Load Output Capacitance Load
Symbol
MSM7583
(VDD = 4.5 V to 5.5 V, Ta = -25C to +70C) Condtion I+, I-, Q+, Q-, ENV I+, I-, Q+, Q-, ENV I+, I-, Q+, Q- (TXW = 0) I+ (CR0 - B5 = 1) when not modulated Q+ (CR0 - B5 = 1) when not modulated ENV (TXW = 0)
ENV (TXW = 1, CR0 - B2 = 0, TXD = 0) ENV (TXW = 1, CR0 - B2 = 1, TXD = 0)
Min. 10 -- 1.55 -- -- -- -- -- 340 -20 -- -- 60 65 -- 0.5 -- -- -- -- --
Typ. -- -- 1.6 1.77 1.67 1.35 1.72 1.63 360 -- 45 4 -- -- 1.0 -- 20 5 2.0 2 400
Max. -- 20 1.65 -- -- -- -- -- 380 +20 -- -- -- -- 3.0 VDD -- -- -- -- --
Unit kW pF V V V V V V mVPP mV mV % dB dB % rms VPP kW pF V kW ms
RLIQ CLIQ VDC1 VDC2
Output DC Voltage Level
VDC3 VDC4 VDC5 VDC6
Output AC Voltage Level Offset Voltage Difference
Output DC Voltage Adjustment Level Range Output AC Voltage Adjustment Level Range
VAC VOFF DCVL ACVL
I+, I-, Q+, Q- (TXW = 0 continuous input) Difference among I+, I-, Q+, and Q- -- --
Out-of-band Spectrum Modulation Accuracy Demodulator IF Input Level IFIN Input Impedance SG Output Voltage SG Output Impedance SG warm-up Time Modulator D/A Conversion Sampling Frequency Modulator D/A Conversion Offset Frequency
P600 600 kHz detuning (*) P900 900 kHz detuning (*) EVM IFV RIF CIF VSG RSG TSG -- IFIN input level -- -- -- -- SGAGND 0.1 mF (Rise Time to 90% of max. level.) FSDA FCDA -- --
-- --
1.92 380
-- --
MHz kHz
* Power attenuation at 600 kHz or 900 kHz 96 kHz as referred to two times of the power in frequency band of 0 to 96 kHz
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Semiconductor Digital Interface Characteristics
Parameter
Symbol
MSM7583
(VDD = 4.5 V to 5.5 V, Ta = -25C to +70C) Condtion Other Min. 200 200 C load = 50 pF Fig. 6 0 0 0 0 Fig. 7 10 10 50 50 50 50 100 C load = 50 pF Fig. 8 50 50 0 50 50 0 -- EXCK -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 200 200 200 -- -- -- -- -- -- -- -- -- 100 -- -- 50 10 ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns MHz Typ. -- -- Max. -- -- Unit ns ns
tSX tXS tDS Transmitter Digital Input/Output Setting Time tDH tXD1 tXD2 tXD3 tXD4 tRD1 Receiver Digital Input/Output Setting Time tRD2 tRS1 to C load = 50 pF tRS4 tRW tM1 tM2 tM3 tM4 Serial Port Digital Input/Output Setting Time tM5 tM6 tM7 tM8 tM9 tM10 tM11 EXCK Clock Frequency fEXCK
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Semiconductor
MSM7583
TIMING DIAGRAM
Transmit Data Input Timing
TXCI [TXCO*] (384 kHz) TXW 1 tXS tSX tDS tDH 1 2 3 N-2 N-1 2 3 N-2 N-1 N N+1 tXS tSX
,, ,,, ,,, ,
TXD
*[ ]: When CR0 - B6 = "1", TXCO is indicated.
Transmit Clock (TXCO) Output Timing (when CR0 - B6 = 1)
TXCI (3.84 MHz) TXCO (384 kHz) 1 tXD1 2 3 4 5 6 tXD2 7 8 9 10 tXD1
Transmit Burst Position Output (BSTO) Timing
TXCI (384 kHz) TXW tXD3 BSTO tXD4 1 2 9 10 N
N+1 N+16 N+17 N+18
Figure 6 Transmit (Modulator) Digital Input/Output Timing
SLS1 SLS2 RCW
AFC RPR RXC tRD1 RXD
tRW
Figure 7 Receiver (Demodulator) Digital Input/Output Timing
,,, ,,, ,,, ,,,
N
tRS1 tRS2 tRS3 tRS4
tRD2
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Semiconductor
MSM7583
DEN tM2 EXCK tM1 1 tM3 2 3 tM6 4 tM7 tM5 5 6 11 12 tM9 tM10
tM4 W/R A2
DIN
A1
A0
B7 tM8
B1
B0 tM11
DOUT
B7
B1
B0
Figure 8 Serial Control Port Interface
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Semiconductor
MSM7583
FUNCTIONAL DESCRIPTION
Control Registers (1) CR0 (basic operation mode setting)
B7 ENVPD CR0 Initial value (*) 0 B6 TXCSEL 0 B5 MODOFF 0 B4 IFSEL1 0 B3 IFSEL2 0 B2 ENVSEL 0 B1 TEST1 0 B0 TEST0 0
* The initial value is set when a reset signal is supplied at RESET.
B7: Transmit envelope output power down control 0/Envelope output ON 1/Envelope output OFF B6: Transmit timing clock selection 0/TXCI input: 384 kHz. TXCO output: 384 kHz output from APLL Transmit data TXD is input in synchronization with the rising edge of TXCI (APLL is on.) 1/TXCI input: 3.84 MHz. TXCO output: 384 kHz (one-tenth of the TXCI frequency) Transmit data TXD is input in synchronization with the rising edge of TXCO (APLL is off.) B5: Modulation on/off control 1/modulation OFF (with phase fixed) 0/modulation ON. B4, B3: Receiver input IF frequency selection (0, 0), (0, 1) : 1.2 MHz (1, 0) : 10.8 MHz (1, 1) : 10.7 MHz/10.75 MHz B2: Transmit envelope (I2 + Q2 or I 2 + Q 2 ) output selection : 0/ I 2 + Q 2 output 1/I2 + Q2 output When B1, B0 is other than (0, 0) : 0/Channel 1 receive monitor output 1/Channel 2 receive monitor output B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin.
I 2 + Q 2 ) output (0, 1): receiver phase detection signal output (1, 0): receiver delay detection signal output (1, 1): receiver internal AFC information output
When B1, B0 is (0, 0)
(0, 0): transmit envelope (I2 + Q2 or
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Semiconductor (2) CR1 (I, Q gain adjustment)
B7 CR1 Initial value Ich GAIN3 0 B6 Ich GAIN2 0 B5 Ich GAIN1 0 B4 Ich GAIN0 0 B3 Qch GAIN3 0 B2 Qch GAIN2 0 B1 Qch GAIN1 0
MSM7583
B0 Qch GAIN0 0
B7 to B4: I+/I- output gain setting, in 3 mV steps (Refer to Table 3.) B3 to B0: Q+/Q- output gain setting, in 3 mV steps (Refer to Table 3.) (3) CR2 (ENV gain adjustment)
B7 CR2 Initial value ENV GAIN3 0 B6 ENV GAIN2 0 B5 ENV GAIN1 0 B4 ENV GAIN0 0 B3 -- 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B4: ENV output gain setting, in 9 mV steps (Refer to Table 3.) B3 to B0: Not used Table 3 I, Q, and ENV Output Gain Values
I and Q Amplitude CR1 B7 B6 B5 B4 (value relative to the reference (1.000) at (0, 0, 0, 0)) B3 B2 B1 B0 0111 1.042 1.036 0110 0101 1.030 0100 1.024 1.018 0011 1.012 0010 0001 1.006 1.000 0000 0.994 1111 0.988 1110 0.982 1101 0.976 1100 0.970 1011 0.964 1010 0.958 1001 0.952 1000 ENV Amplitude (value relative to the reference (1.000) at (0, 0, 0, 0)) 1.126 1.108 1.090 1.072 1.054 1.036 1.018 1.000 0.982 0.964 0.946 0.928 0.910 0.892 0.874 0.856
CR2 B7 B6 B5 B4 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000
18/23
Semiconductor (4) CR3 (I- output offset voltage adjustment)
B7 CR3 Initial value Ich Offset4 0 B6 Ich Offset3 0 B5 Ich Offset2 0 B4 Ich Offset1 0 B3 Ich Offset0 0 B2 -- 0 B1 -- 0
MSM7583
B0 -- 0
B7 to B3: I- output pin offset voltage adjustment (Refer to Table 4.) B2 to B0: Not used (5) CR4 (Q- output offset voltage adjustment)
B7 CR4 Initial value Qch Offset4 0 B6 Qch Offset3 0 B5 Qch Offset2 0 B4 Qch Offset1 0 B3 Qch Offset0 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B3: Q- output pin offset voltage adjustment (Refer to Table 4.) B2 to B0: Not used Table 4 I and Q Channel Offset Adjustment Values
CR3, CR4 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B5 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B4 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 I and Q offset (mV) +45 +42 +39 +36 +33 +30 +27 +24 +21 +18 +15 +12 +9 +6 +3 0 B7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B6 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CR3, CR4 B5 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B4 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 I and Q offset (mV) -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
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Semiconductor (6) CR5 (IC test)
B7 CR5 Initial value ICT7 0 B6 ICT6 0 B5 ICT5 0 B4 ICT4 0 B3 LOCAL INV1 0 B2 LOCAL INV0 0 B1 ICT1 0
MSM7583
B0 ICT0 0
B7 to B4: ICT7 to ICT4. Device test control bits. B3, B2 : Local inverting mode setting bits. (Used when the phase of the demodulator IF input to this device is inverted.) (1, 1) = local inverting mode (0, 0) = normal mode B1, B0 : ICT1, ICT0. Device test control bits. Note: CR5 - B7 to B4, B1, and B0 are used to test the device. They should be set to "0" during normal operation.
State Transition Time
Note: The transition time is 1 ms or less unless otherwise stated Mode A
5 ms
1 ms Mode B PDN1 = 0 PDN2 = 1 PDN1 = 0 PDN2 = 0
Standby mode (PDN0 = 0) Communication mode (PDN0 = 1) 40 ms Mode D PDN1 = 1 PDN2 = 0 5 ms
5 ms Mode C PDN1 = 0 PDN2 = 0 40 ms Mode F PDN1 = 1 PDN2 = 1 Mode E PDN1 = 0 PDN2 = 1
Figure 9 Power-Down State Transition Time
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Semiconductor
MSM7583
APPLICATION CIRCUIT
Demodulator 1 control signal Demodulator 2 control signal Receive symbol clock output Receive clock output Receive data output Receive channel select signal Receive symbol clock 2 output Receive clock 2 output Receive data 2 output
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 RXC2
AFC2
AFC1
RXSEL
NC
RCW2
RCW1
RPR1
RXD0
RPR2
RXSC0
1 2 19.2 MHz input C5 Demodulator 2 IF input Demodulator 1 IF input VDD
Control register control signal
RXSC2
RXD2
X2
X1
RXC0
49
NC IFCK MCK DGND IFIN2 DGND IFIN1 DGND VDD DOUT DIN EXCK DEN RESET PDN0
PDN2 BSTO
NC
48 47 46 45 44 43 42 41 40 39 38 VDD 37 36 35 34 33 C3 C2 Modulator Q component output Modulator I component output VDD C1 Demodulator 2 control signal Receive symbol clock 1 output Receive clock 1 output Receive data 1 output Demodulator 1 control signal
To orthogonal modulator
SLS22 SLS12 RXSC1 RXC1 RXD1 SLS21 SLS11 VDD ENV Q- Q+ I- I+ SG
TXCO TXCI TXW
3 4 5 6 7 8 9 10 11 12 13 14 15 16
C4
MSM7583GS-BK
Reset signal Power down control signal
PDN1
NC
AGND
NC NC NC NC NC NC NC 30 NC 31 NC 32
17
18
19
20
21
TXD
22
23
24
25
26
27
28
Burst window output Modulator data window Modulator input data Modulator 384 kHz input
29
C1 = 10 mF C2 = C3 = 0.1 mF C4 = C5 = 1000 pF
Figure 10 Example of Circuit Configuration
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Semiconductor Demodulator Control Timing Diagram (Example)
Demodulator unit Modulator input data Timing for CS PDN2 SLS2 SLS1 AFC Slot 1
R1
MSM7583
RXD RXC
(1) Control channel/synchronous burst (SS + PR = 64 bits)
RXD AFC
, , , ,
Slot 2
R2
Slot 3
R3
Slot 4
R4
G
G
G
G
G
"0" "0"
"0" "1"
"1" "0"
"1" "1"
R1
R2
R3
R4
240 bits 625 ms
64 bits
G G G G G G G G R R R R SS SS PR PR
-------------
PR UW
-------------
CR CR G G G G G G G G
RPR RCW 56 bits
(2) Communication channel (SS + PR = 8 bits) RXD AFC RPR RCW "0"
8 bits
------------CR CR G G G G G G G G
G G G G G G G G R R R R SS SS PR PR ----- PR UW
Loss than 30 bits
G: Guard bit R: Ramp bit SS: Start symbol bit PR: Preamble bit UW: Unique word bit CR: CRC bit
* AFC and RCW may be controlled at the same timing.
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Semiconductor
MSM7583
PACKAGE DIMENSIONS
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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